When Power is Paramount

Low power design has become THE critical issue for SoC developers. Many applications demand reduced power consumption in the form of both lower standby power and substantial cuts in dynamic power as the trend towards “always-on” accelerate. Innovative IoT, wearables, medical, mobile, automotive and networking products all require sureCore’s power optimised SRAM technologies. sureCore IP is silicon-proven, process independent, variability tolerant and features market leading dynamic & static power consumption thanks to advanced sleep modes that provide greater system level flexibility.
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PowerMiser – sureCore’s Single Port Synchronous Low Power SRAM IP delivers more than 50% dynamic power savings and approximate 20% static power savings compared to industry standard SRAMs. Performance comparable, sureCore’s low power products are ideal for replacing current SRAM IP and delivering SoC-wide power benefits. sureCore IP is process agnostic and has been silicon proven in 40ULP BULK CMOS and 28nm FDSOI manufacturing processes.

EverOn – sureCore’s Single Port Synchronous Ultra Low Voltage SRAM IP targets applications for where driving down power consumption is critical including “Keep Alive” design scenarios. Leveraging our “SMART-Assist” technology enables SRAM operation at near-threshold bit cell retention voltages. In 40nm operation from 1.2V down to 0.6V has been demonstrated across temperature. Powerful features such as multiple independent memory banks coupled with extensive power down options provide system architects with unrivalled flexibility. Silicon proven on 40ULP BULK CMOS process technology the compiler is available now.

PowerMiser

sureCore’s Low Power SRAM IP has been developed for leading-edge devices demanding long battery life and minimal operating and stand-by power consumption. PowerMiser products have been realized in both 28nm FDSOI and 40ULP BULK CMOS manufacturing processes.

This Low Power macro operates in an extreme low voltage range of 0.7v to 1.2v where it demonstrated dynamic power savings exceeding 50% of current commercial instances. The IP has also demonstrated leakage power savings ranging from 38% to 21%, depending on current conditions, while incurring only a small 10% area penalty.

The compilers supports capacities up to 576Kbit with word lengths up to 144bits with three multiplexing factors; 4, 8 and 16. The compiler allows designers to make trade-offs between various SRAM sizes in terms of number of words, word length and multiplex factor. It automatically generates datasheets, simulation (Verilog), layout (LEF) and timing/power (Liberty) models to enable standard EDA tool flows.

Product Performance
PowerMiser delivers best-in-class static and dynamic power performance. Its patented “Bit Line Voltage Control” techniques have the added benefit of virtually eliminating performance compromises at low operating voltages. Retentive sleep modes, including light sleep for rapid wake-up as well as deep-sleep for maximal leakage current savings, are offered.

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EverOn

sureCore’s Single Port Ultra Low Voltage (ULV) SRAM IP is silicon-proven on 40ULP BULK CMOS process and provides up to 80% savings in dynamic power consumption and an up to 75% reduction in static power.

The memory operates down to a record-setting 0.6V across process, voltage and temperature delivering an impressive operating voltage range from 0.6V to 1.21V. It provides an unprecedented 20MHz cycle time at 0.6V scaling to over 300MHz at 1.21V, opening new capabilities for cutting edge wearable and Internet of Things applications.

The ULV compiler supports synchronous single port SRAM with operating voltages ranging from 0.6 to 1.21 volts and memory capacities ranging from 8Kbytes to 576Kbytes with maximum word lengths of 72bits.

Product Performance
EverOn meets the challenges posed by dynamic voltage and frequency scaling (DVFS). Built using high-density foundry bit cells to reduce area, a single supply rail implementation eases integration.

sureCore’s “SMART-Assist” technology allows robust operation down to the retention voltage. Further architectural innovations include subdividing the memory into up to eight banks, which in conjunction with enhanced sleep modes, provide greater system level flexibility. As well as operating in peripheral power off, light and deep sleep modes, each bank can also be independently controlled for active or in light sleep, deep sleep or power off modes. These power saving modes provide greater flexibility to tailor product performance around operational needs and extend battery life.

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When Power is Paramount

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