SureCore’s vision is driven by an insatiable desire to extend operating life of “Always-on /Keep-alive” circuitry from days and weeks to months and years. These new ‘green and sustainable’ application requirements characterizes the next generation of semiconductors, particularly SoC designs. One of the most daunting technical challenges is to support limited data processing at previously unattainably low operating voltages so that even in ‘always on’ mode, the majority of the SoC is powered off while awaiting an activation event.
While tablet and smartphone sales have declined, the IoT market is exploding and is predicted to deliver a compounded annual growth rate of nearly 36% between 2016 and 2020, according to Dublin-based Research and Markets. Although the IoT market leads the drive for more power savings the same requirements are equally critical in the medical diagnostics segment, where in-service costs are significantly impacted by battery life and battery replacement.
The emergence of low power electronics also opens opportunities for energy scavenging technologies to replace or augment batteries, thus giving rise to more intelligent power supply systems. This trend extends beyond the traditional circuits approach into the incorporation of system solutions to limit power. This feature is particularly relevant today as new wireless technologies are explored that will improve spectrum efficiency but the higher the operating frequency will place greater demands on battery management.
Because of the “always-on /keep-alive” nature of IoT applications, more and more attention is being paid to the integrated circuits (IC’s) that at the core. In the emerging IoT market, the majority of SoCs are event driven; powered off until an external stimulus awakes them. Normally this requires the built-in processor and SRAM memory to undertake limited processing and operate at lowest possible voltage. However, using today’s technology, this is not possible for many applications. The processor and SRAM’s dynamic and static power consumptions are too high because the operating speed envelope is too wide and the available power-down modes lack sufficient granularity and flexibility.
SureCore’s ultra-low power SRAM development hypothesis was to revisit the power consumption ‘facts’ at the most basic level, challenging and questioning fundamental and well-adopted SRAM design trade-offs. This started at the SRAM architecture level and resulted in dramatically reducing dynamic power. A basic redesign of the power-down modes now manages static power consumption by banking memories to control flexibility while retaining all-important retention performance enabled a solution capable of operating from 1.21 volts down to 0.6 volts .
sureCore’s Smart Assist technology addresses both the flexibility of memory power control and a reduced minimum operating voltage.
Today, sureCore’s ultra-low power SRAM IP portfolio includes process-independent macros that are silicon proven on 40ULP BULK CMOS process and ST’s 28nm FDSOI process technologies. Innovative sleep modes provide greater system level flexibility and extended capacities from 512×16 to 8Kx72 solutions are available. Static power consumption has been reduced to less than 160nW, while the maximum operating frequency exceeds 300MHz.
However this is just the start. SureCore continue to take advantage of technology advances to develop IP that exploits the underlying technology benefits and promises for even greater power reduction in the future.