sureCore, the ultra-low power embedded IP specialist
Analogue/Mixed Signal Design
Our highly experienced engineering team can Our analogue/mixed-signal design services provide, with a strong emphasis on low-power design to meet the demands of modern, energy-efficient applications. We specialize in creating power-optimized solutions for a wide range of products, including IoT devices, edge-AI, wearables, medical devices, and sensor interfaces—where minimizing energy consumption is critical. Our expertise spans analog front-end design, low-power data converters (ADCs/DACs), phase-locked loops (PLLs), bandgaps, DC to DC converters ensuring high performance with minimal power draw.
With extensive experience designing across a broad range of process nodes—from mature technologies at 180nm down to cutting-edge nodes at 4nm—we offer tailored solutions optimized for each technology generation. Our deep understanding of process-specific design challenges, such as variability in advanced nodes as well as leakage reduction, enables us to deliver highly efficient designs suited to the unique demands of each node. We leverage the strengths of mature nodes (e.g., 180nm, 130nm, and 65nm) for cost-sensitive and analog-centric applications while utilizing advanced nodes (e.g., 28nm, 16nm, 7nm, and 4nm) for power-sensitive and high-integration designs.
Our experience spans multiple leading foundries, including TSMC, GlobalFoundries, and Samsung, allowing us to help customers navigate different process technologies, design kits, and PDKs. This multi-foundry expertise enables us to optimize designs for process portability, yield, and cost-efficiency while maintaining consistent performance and reliability. Additionally, we have deep expertise in Fully Depleted Silicon-on-Insulator (FD-SOI) technology, which is ideal for ultra-low-power and low-voltage applications. Leveraging the inherent advantages of FD-SOI, such as reduced leakage current and improved body-biasing capabilities, we develop designs that achieve exceptional power efficiency and performance at lower operating voltages, making FD-SOI an optimal choice for IoT, automotive, and wearable applications.
Our engineers leverage sophisticated simulation, statistical analysis, and verification methodologies to achieve optimal signal integrity, low noise, and efficient power management under varying operating conditions.
With deep experience across process nodes down to 4nm, we address the unique power challenges of advanced technologies, such as leakage current reduction, thermal management, and ultra-low-voltage operation. Our end-to-end services cover every phase of the design lifecycle—from architecture and schematic development to layout, low-power verification, and post-silicon validation—ensuring our customers meet their performance and power targets without compromising reliability.
By prioritizing power efficiency at every design stage and leveraging our expertise across multiple foundries and FD-SOI technology, we help customers bring cutting-edge mixed-signal solutions to market that are optimized for low power, enabling longer battery life, reduced heat dissipation, and sustainable, energy-efficient products across a broad spectrum of industries and applications.
Full Custom Transistor Level Layout
Our **Full Custom Transistor-Level Layout** services provide highly optimized, performance-driven layout solutions tailored to meet the most demanding design specifications. With deep expertise in analog, digital, and mixed-signal design, our team delivers fully customized layouts that maximize area efficiency, minimize parasitic effects, and achieve superior power and performance metrics. We have extensive experience in designing sensitive analog blocks, such as amplifiers, data converters (ADCs/DACs), PLLs, and power management circuits, where precise device matching, symmetry, and shielding are critical.
Our layouts are meticulously crafted with advanced techniques, including common-centroid structures, interdigitated device arrays, and carefully balanced routing, ensuring excellent matching and reducing variability. We apply comprehensive Design for Manufacturability (DFM) practices to enhance yield and reliability, incorporating techniques such as dummy device insertion, guard rings, and well proximity effect (WPE) mitigation.
With experience across process nodes from **180nm to 4nm**, including **FD-SOI** and **FinFET technologies**, we are skilled in addressing the challenges of advanced nodes, such as minimizing leakage currents, managing variability, and optimizing for low power. Additionally, our proficiency in working with multiple foundries, including TSMC, GlobalFoundries and Samsung ensures that our layouts are compliant with foundry-specific design rules and process design kits (PDKs).
We integrate comprehensive post-layout simulations, including parasitic extraction (PEX) and layout-versus-schematic (LVS) verification, to ensure first-pass silicon success. Our commitment to low-power design is reflected in every aspect of the layout, from device-level optimizations to power grid design and electromigration (EM) analysis.
By combining precision craftsmanship with advanced design techniques, our full custom transistor-level layouts deliver superior performance, power efficiency, and reliability—empowering our customers to achieve their design goals and accelerate time-to-market.
Mixed Signal Verification & Characterisation
Our Mixed-Signal Verification and Characterization services ensure the functionality, performance, and robustness of complex analog-digital designs, accelerating time-to-market with high confidence in silicon success. We provide comprehensive pre-silicon verification and post-silicon characterization, covering a wide range of mixed-signal blocks such as ADCs, DACs, PLLs, power management circuits, and sensor interfaces.
Our pre-silicon verification employs advanced simulation techniques, including AMS (Analog Mixed-Signal) simulation, behavioral modeling using Verilog-AMS, Our verification strategy also includes comprehensive checks such as functional verification, noise analysis, and jitter simulations to ensure the design meets performance and power specifications under all operating conditions.
Post-silicon, we conduct thorough characterization and validation across process, voltage, and temperature (PVT) corners, ensuring the design meets the required specifications in real-world conditions. Our characterization process includes measuring critical parameters such as gain, offset, linearity (INL/DNL), phase noise, and power consumption. We use custom-designed test setups, automated test equipment (Labview), and lab instrumentation** to ensure accurate measurements and efficient data collection.
By integrating pre-silicon verification with rigorous post-silicon characterization, we provide a comprehensive solution that reduces risk, shortens debug cycles, and ensures high-performance, low-power mixed-signal designs are production-ready with first-pass success.
Test Chip Development & Evaluation
Our Test Chip Development services enable customers to validate new designs, IP blocks, and process technologies through comprehensive silicon prototyping. We provide end-to-end support, from architecture definition to tape-out and post-silicon evaluation, ensuring that critical design elements are thoroughly tested before full-scale production. Our expertise spans custom analog, digital, and mixed-signal IP blocks, including ADCs, DACs, PLLs, SerDes, and power management circuits, allowing customers to assess functionality, performance, and power efficiency in real silicon.
We develop multi-project wafer (MPW) test chips, enabling cost-effective prototyping and efficient reuse of wafer space for multiple IPs. Our design-for-test (DFT) methodologies include on-chip test structures, scan chains, and built-in self-test (BIST) circuits to facilitate thorough functional and parametric testing. Additionally, we incorporate process monitors (e.g., ring oscillators and voltage/current references) to characterize the process technology across PVT (process, voltage, temperature) corners.
With extensive experience designing on process nodes from 180nm down to 4nm, including FD-SOI and FinFET technologies, we address advanced-node challenges such as variability, leakage, and electromigration (EM). Our multi-foundry experience with TSMC, GlobalFoundries, and Samsung ensures smooth integration with foundry-specific tape-out and test flows.
Post-silicon, we manage the test chip bring-up, characterization, and data analysis, using automated test equipment (Labview) and custom lab setups to gather performance metrics such as linearity (INL/DNL), jitter, power efficiency, and timing margins. We analyze results to correlate pre-silicon simulations with measured silicon performance, providing valuable feedback for IP refinement and process optimization.
Through our comprehensive test chip development services, customers gain early silicon insights, reduce risk, and accelerate their path to first-pass silicon success for production designs.